The present invention relates to the field of multiplier circuits, and more particularly, to the field of four-quadrant analog multiplier circuits.
Analog multiplier circuits form important building blocks for devices such as adaptive filters, function generators, and modulators. In the emerging field of artificial neural networks, implementation of useful network structures in analog integrated circuitry will in many cases require large arrays of multipliers.
One type of multiplier is described in U.S. Pat. No. 4,978,873, by Shoemaker, entitled "CMOS Analog Four-Quadrant Multiplier." This multiplier provides four-quadrant multiplication of two values represented by input voltages, V.sub.1 and V.sub.2, which are applied to the transistors. The output of the circuit is proportional to the product (V.sub.1 V.sub.2).
One embodiment of this type of multiplier includes a complementary pair of n- and p-channel transistors. The respective threshold voltages V.sub.tn and V.sub.tp of the n- and p-channel transistors satisfy the relation: V.sub.tp -V.sub.tn &gt;0. The gates of the two transistors are connected in common and receive a voltage which is the sum of input V.sub.1 and a bias voltage V.sub.b, where V.sub.b =(V.sub.tp +V.sub.tn)/2. The bias voltage, V.sub.b, eliminates offset in the circuit output due to threshold voltage magnitude mismatch. Second voltage input V.sub.2 and its inverse -V.sub.2 are also provided to the circuit. In the case where V.sub.2 &gt;0, V.sub.2 is provided to the terminal of the n-channel transistor which acts as the drain and -V.sub.2 is provided to the terminal of the p-channel transistor which acts as the drain. The terminals of each transistor which act as sources are connected at an output node. In the case where V.sub.2 &lt;0, then V.sub.2 and -V.sub.2 are applied to the same physical terminals as in the first case, however, these two terminals become the sources of the two transistors due to the difference in polarity of the applied voltages from those of the first case. In the latter case, the two terminals which are connected at the output node become the drains of the two transistors. In either case, the circuit provides an output proportional to the product (V.sub.1 V.sub.2).
A second embodiment of the multiplier described in U.S. Pat. No. 4,978,873 includes two pairs of complementary MOS transistors, where each pair is configured similarly to the circuit of the first embodiment, except that the inputs V.sub.1, V.sub.2, and -V.sub.2 are replaced by their inverses -V.sub.1, -V.sub.2 , and V.sub.2, respectively, on one of the two pairs. The output nodes of the individual transistor pairs are connected in common. The bias voltage used in this circuit may deviate significantly from that of the first embodiment as the error which such a deviation would cause in the first embodiment is canceled in the second. However, a disadvantage of this embodiment is that it requires two pairs of transistors and the inverse -V.sub.1 of the voltage V.sub.1.
A limitation of the above-referenced four-quadrant multiplier is that it requires matching of the transconductance constants of the n- and p-channel MOSFET's. If transistors without such matching are used in the circuit, nonlinearities and additional offsets are introduced, resulting in distortion in the circuit output. Such mismatches can result from the manufacturing processes by which the transistors are fabricated, or from temperature, radiation, or aging effects.
Therefore, there is a need for a circuit that compensates for mismatches in both transistor threshold voltage magnitudes and transconductance constants.